1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a semiconductor memory device such as a dynamic random access memory which is hereinafter refereed to as a DRAM.
Priority is claimed on Japanese Patent Application No. 2008-280106, filed Oct. 30, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, semiconductor memory devices such as DRAMs have been increasing in its capacity, while increasing the cost for testing wafer. There are techniques to avoid the increase in the cost for testing wafer. Japanese Unexamined Patent Application, First Publication, No. JP-A-2001-338953 discloses a technique for avoiding the increase in the cost for testing wafer, wherein a plurality of chips is measured at the same time. Japanese Unexamined Patent Application, First Publication, No. JP-A-2000-11695 discloses a parallel test technique that compresses a plurality of bits into one bit and outputs the compressed bit to the outside of a chip in order to reduce the test time.